REV. 1.2.1 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 33 EMSR[5:4]: Extended RTS Hysteresis EMSR[6]: LSR Interrupt Mode
參數(shù)資料
型號(hào): XR16L2752IJ-F
廠(chǎng)商: Exar Corporation
文件頁(yè)數(shù): 27/49頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 64B DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線(xiàn))
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱(chēng): 1016-1650
XR16L2752IJ-F-ND
xr
XR16L2752
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
33
EMSR[5:4]: Extended RTS Hysteresis
EMSR[6]: LSR Interrupt Mode
Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an
interrupt when the character with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: 16X Sampling Rate Mode
Logic 0 = 8X Sampling Rate.
Logic 1 = 16X Sampling Rate (for 16C2550 compatibility, default).
4.13
FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is
not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12 for details.
TABLE 13: RTS Hysteresis Levels
EMSR
BIT-5
EMSR
BIT-4
FCTR
BIT-1
FCTR
BIT-0
RTS# HYSTERESIS
(CHARACTERS)
0
1
±4
0
1
0
±6
0
1
±8
0
1
0
±8
0
1
0
1
±16
0
1
0
±24
0
1
±32
1
0
±40
1
0
1
±44
1
0
1
0
±48
1
0
1
±52
1
0
±12
1
0
1
±20
1
0
±28
1
±36
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