xr
XR16L2752
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
21
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
0 0 0
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
0 0 0
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
IER
RD/WR
0/
Modem
Stat.
Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
CTS Int.
Enable
RTS Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0
ISR
RD
FIFOs
Enabled
FIFOs
Enabled
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
INT
Source
Bit-5
INT
Source
Bit-4
0 1 0
FCR
WR
RXFIFO
Trigger
RXFIFO
Trigger
0/
DMA
Mode
Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
TXFIFO
Trigger
TXFIFO
Trigger
0 1 1
LCR
RD/WR Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0
MCR
RD/WR
0/
Internal
Lopback
Enable
OP2#
Output
Control
Rsrvd
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LCR
≠ 0xBF
BRG
Pres-
caler
IR Mode
ENable
XonAny
1 0 1
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Fram-
ing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
1 1 1
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR
≠ 0xBF
FCTR bit-6=0
1 1 1
EMSR
WR
16X
Sam-
pling
Rate
Mode
LSR
Error
Inter-
rupt.
Imd/Dly#
Auto
RTS
Hyst.
bit-3
Auto
RTS
Hyst.
bit-2
Auto
RS485
Output
Inver-
sion
Rsrvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR
≠ 0xBF
FCTR bit-6=1
1 1 1
FLVL
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0