參數(shù)資料
型號(hào)： XR16L784IV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 14/51頁(yè)
文件大?。?/td> 0K
描述： IC UART 8B 3.3V QUAD 64LQFP
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
其它名稱： 1016-1282
XR16L784
21
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
3.1.1
The Global Interrupt Source Registers
The XR16L784 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. Register INT3 is not used in the 784 UART, only in the 8-channel XR16L788. The 3 registers
are in the device configuration register address space.
All 4 registers default to logic zero (as indicated in square braces) for no interrupt pending. All 4 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1 and INT2 show the details of the source of each channel’s interrupt with its unique 3-bit
encoding. Figure 14 shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep wake-
up interrupts are masked in the device configuration registers, TIMERCNTL and SLEEP. An interrupt
is
generated by the 784 when awakened from sleep if all 4 channels were placed in the sleep mode previously.
Reading INT0 will clear this wake-up interrupt.
Each bit in the INT0 register gives an indication of the channel that has requested service.
3.1.1.1
INT0 Channel Interrupt Indicator:
For example, bit-0 represents channel 0 and bit-3 indicates channel 3. Bits 4 to 7 are reserved and remains at
logic zero. Logic one indicates the channel N [3:0] has called for service. The interrupt bit clears after reading
the appropiate register of the interrupting UART channel register (ISR, LSR and MSR). See Table 13 for
interrupt clearing details.
3.1.1.2
INT1 and INT2 Interrupt Source Locator
INT2 and INT1 provide a 12-bit (3 bits per channel) encoded interrupt indicator. Table 9 shows the 3 bit
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt .
For other channels, interrupt 7 is reserved.
.
INT3 (Rsvd)
[0x00]
INT2
[0x00]
INT1
[0x00]
INT0
[0x00]
FIGURE 14. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
INT0 Register
Individual UART Channel Interrupt Status
Rsvd
Ch-3
Ch-2
Ch-1
Ch-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Reserved
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
INT0 Register
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Rsvd
Ch-3
Rsvd
Ch-2
Ch-1 Ch-0
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