FIGURE 22. T
參數(shù)資料
型號: XR16L784IV-F
廠商: Exar Corporation
文件頁數(shù): 42/51頁
文件大小: 0K
描述: IC UART 8B 3.3V QUAD 64LQFP
標(biāo)準(zhǔn)包裝: 160
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 1016-1282
XR16L784
47
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
FIGURE 22. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]
FIGURE 23. RECEIVE INTERRUPT TIMING [FIFO MODE]
FIGURE 24. TRANSMIT INTERRUPT TIMING [FIFO MODE]
TX
IO W #
IN T # *
D0 :D 7
Sta rt
Bit
D0 :D 7
Sto p
Bit
D0 :D 7
T
WR I
T
WR I
T
WR I
* T X in te rrupt is c leared w h en the IS R is read or w hen data is loade d in to the TH R .
IS R is re a d
(Loa ding d a ta
in to T H R )
(U nloa ding)
IE R [1 ]
enab le d
RX
IO R#
INT#
D0:D7
S
RX FIFO fills up to RX
Trigger Level or RX Data
Tim eout
RX FIFO drops
below RX
Trigger Level
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
T
RR
T
RR I
T
SSI
(Reading data out
of RX FIFO )
TX
IO W #
IN T#*
D0:D 7
S
D0:D 7
T
D0:D 7
S
D0:D 7
S
T
D0:D 7
S
T
D0:D 7
S
T
Start
Bit
Stop
Bit
(U nloading)
(Loading data
into FIFO )
Last D ata B yte
Transm itted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TX FIFO
Em pty
T
S
T
SI
IS R is read
IE R [1]
enabled
IS R is read
*TX interrupt is cleared when the IS R is read or when TX FIFO fills up to the trigger level.
T
WR I
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