TABLE 12: UART CHANNEL " />
參數(shù)資料
型號: XR16L784IV-F
廠商: Exar Corporation
文件頁數(shù): 19/51頁
文件大小: 0K
描述: IC UART 8B 3.3V QUAD 64LQFP
標準包裝: 160
特點: *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 1016-1282
XR16L784
26
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
0 0 0 0
RHR
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0 0
THR
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=0
0 0 0 0
DLL
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 0 1
DLM
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
0 0 0 1
IER
R/W
0
Modem
Status
Int.
Enable
RX Line
Status
Int.
Enable
TX
Empty
Int.
Enable
RX Data
Int.
Enable
CTS/
DSR# Int.
Enable
RTS/
DTR# Int.
Enable
Xon/Xoff/
Sp. Char.
Int.
Enable
0 0 1 0
ISR
R
FIFOs
Enable
FIFOs
Enable
0
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
Delta-
Flow
Cntl
Xoff/spe-
cial char
0 0 1 0
FCR
W
RXFIFO
Trigger
RXFIFO
Trigger
TXFIFO
Trigger
TXFIFO
Trigger
DMA
Mode
TX FIFO
Reset
RX FIFO
Reset
FIFOs
Enable
0 0 1 1
LCR
R/W
Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Enable
Stop Bits
Word
Length
Bit-1
Word
Length
Bit-0
0 1 0 0
MCR
R/W
0
Internal
Lopback
Enable
OP22
OP12
RTS#
Pin Con-
trol
DTR#
Pin Con-
trol
BRG
Pres-
caler
IR
Enable
XonAny
RTS/
DTR
Flow Sel
0 1 0 1
LSR
R/W
RX FIFO
ERROR
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX Par-
ity Error
RX
Overrun
RX Data
Ready
0 1 1 0
MSR
R
CD
RI
DSR
CTS
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
MSR
W
RS485
DLY-3
RS485
DLY-2
RS485
DLY-1
RS485
DLY-0
0
0 1 1 1
SPR
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
User Data
1 0 0 0
FCTR
R/W
TRG
Table
Bit-1
TRG
Table
Bit-0
Auto
RS485
Enable
Invert IR
RX Input
RTS/
DTR
Hyst Bit-
3
RTS/
DTR
Hyst Bit-
2
RTS/
DTR
Hyst Bit-
1
RTS/
DTR
Hyst Bit-
0
1 0 0 1
EFR
R/W
Auto
CTS/
DSR
Enable
Auto
RTS/
DTR
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
MSR[7:4]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
1 0 1 0
TXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 0
TXTRG
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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