參數(shù)資料
型號: XR16L788CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE OCTAL UART
中文描述: 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁數(shù): 10/42頁
文件大?。?/td> 557K
代理商: XR16L788CQ
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XR16L788 OCTAL UART
REV. 1.1.4
10
1.1.2
[TIMERMSB, TIMELSB, TIMER, TIMECNTL]
(
DEFAULT
0
X
XX-XX-00-00)
A 16-bit down-count timer for general purpose timer
or counter. Its clock source may be selected from in-
ternal crystal oscillator or externally on pin TMRCK.
The timer can be set to be a single-shot for a one-
time event or re-triggerable for a periodic event. An
General Purpose 16-bit Timer/Counter.
interrupt may be generated in the INT Register when
the timer times out. It is controlled through 4 configu-
ration registers [TIMERCNTL, TIMER, TIMELSB,
TIMERMSB]. These registers provide start/stop and
re-triggerable or one-shot operation. The time-out
output of the Timer can be set to generate an inter-
rupt for system or event alarm.
T
ABLE
3: UART C
HANNEL
[7:0] I
NTERRUPT
S
OURCE
E
NCODING
AND
C
LEARING
P
RIORITY
B
IT
2B
IT
1 B
IT
0
I
NTERRUPT
S
OURCE
(
S
)
AND
C
LEARING
x
1
0
0
0
0
0
1
None
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
RXRDY Time-out: Cleared same way as RXRDY INT.
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two clears
after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR register.
Reserved.
Reserved.
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
Reserved in other channels.
2
3
4
0
0
1
1
1
0
0
1
0
5
6
7
1
1
1
0
1
1
1
0
1
F
IGURE
5. T
IMER
/C
OUNTER
CIRCUIT
.
TMRCK
OSC. CLOCK
TIMERCNTL [3]
16-Bit
Timer/Counter
TIMERCNTL [2]
Re-trigger
Single-shot
TIMERCNTL [1]
Start/Stop
TIMERCNTL [0]
Timer Interrupt, Ch-0 INT=7
No Interrupt
Time-out
Timer Interrupt Enable
Single/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
0
1
0
1
Clock
Select
T
ABLE
4: TIMER CONTROL R
EGISTER
TIMERCNTL [0]
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
Reserved (defaults to zero).
TIMERCNLT [1]
TIMERCNTL [2]
TIMERCNTL [3]
TIMERCNTL [7:4]
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