參數(shù)資料
型號(hào): XR16L788CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE OCTAL UART
中文描述: 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, 3 MM HEIGHT, PLASTIC, QFP-100
文件頁(yè)數(shù): 15/42頁(yè)
文件大?。?/td> 557K
代理商: XR16L788CQ
XR16L788 OCTAL UART
á
REV. 1.1.4
15
- Enable RTS/DTR interrupt through IER bit-6 (after
setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR
bit-5 will be set to 1.
- Select Hysteresis values when used with program-
mable RX FIFO trigger levels
4.2.1
Auto CTS/DSR Flow Control
Automatic CTS/DSR flow control is used to prevent
data overrun to the remote receiver FIFO. The CTS/
DSR pin is monitored to suspend/restart local trans-
mitter. The flow control features are individually se-
lected to fit specific application requirement (see
Figure 8):
- Select CTS (and RTS) or DSR (and DTR) through
MCR bit-2.
- Enable auto CTS/DSR flow control using EFR bit-7.
- Enable CTS/DSR interrupt through IER bit-7 (after
setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR
bit-5 will be set to 1, and UART will suspend TX
transmissions as soon as the stop bit of the charac-
ter in process is shifted out. Transmission is re-
sumed after the CTS#/DSR# input returns to logic
0, indicating more data may be sent.
F
IGURE
8. A
UTO
RTS/DTR
AND
CTS/DSR F
LOW
C
ONTROL
O
PERATION
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit
shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA
re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next re-
ceive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB#
and CTSA# controlling the data flow.
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
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