REV. 1.0.0 Each bit gives an indication of the channel that has reques" />
參數(shù)資料
型號(hào)： XR16M698IQ-0B-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 19/58頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR M698-B 100QFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M698
26
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
REV. 1.0.0
Each bit gives an indication of the channel that has requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate register of the interrupting UART channel register (ISR, LSR
and MSR). SEE”INTERRUPT CLEARING:” ON PAGE 35. for interrupt clearing details.
3.1.1.1
INT0 Channel Interrupt Indicator
INT0 Register
Individual UART Channel Interrupt Status
Ch-7
Ch-6
Ch-5 Ch-4
Ch-3 Ch-2
Ch-1 Ch-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3 Bit-2
Bit-1
Bit-0
3.1.1.2
INT1, INT2 and INT3 Interrupt Source Locator
INT3, INT2 and INT1 provide a 24-bit (3 bits per channel) encoded interrupt indicator. Table 10 shows the 3 bit
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt.
For other channels, interrupt 7 is reserved.
.
FIGURE 13. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
Channel-7
Channel-6
Channel-5
Channel-4
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
Bit
1
Bit
2
Bit
0
INT0 Register
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-6
Ch-7
Ch-5 Ch-4
Ch-1 Ch-0
Ch-3 Ch-2
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相關(guān)代理商/技術(shù)參數(shù)
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