FIGURE 20. TRANSMIT I
參數(shù)資料
型號(hào): XR16M698IQ-0B-EVB
廠商: Exar Corporation
文件頁數(shù): 51/58頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR M698-B 100QFP
標(biāo)準(zhǔn)包裝: 1
系列: *
FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]
TX
IO W #
IN T # *
D0 :D 7
Sta rt
Bit
D0 :D7
Sto p
Bit
D0 :D 7
T
WR I
T
WR I
T
WR I
*T X interrupt is c leared w h en the IS R is read or w hen data is loade d into the TH R .
IS R is re a d
(Loa ding d ata
in to T H R )
(U nloa ding)
IE R [1 ]
enab led
FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]
RX
IOR#
INT#
D0:D7
S
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
T
RR
T
RRI
T
SSI
(Reading data out
of RX FIFO)
FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]
TX
IO W #
INT#*
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
(Unloading)
(Loading data
into FIFO )
Last Data Byte
Transm itted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
TX FIFO
Em pty
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
*TX interrupt is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
T
WR I
XR16M698
55
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
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