REV. 1.0.0 MSR[6]: RI Input Status Normally this bit is the complement" />
參數(shù)資料
型號： XR16M698IQ-0B-EVB
廠商： Exar Corporation
文件頁數(shù)： 37/58頁
文件大小： 0K
描述： EVAL BOARD FOR M698-B 100QFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M698
42
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
REV. 1.0.0
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS/DSR bit (EFR bit-6=1) and RTS/DTR flow control select bit (MCR bit-2=1). Auto CTS/DSR flow control
allows starting and stopping of local data transmissions based on the modem DSR# signal. A HIGH on the
DSR# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW
will resume data transmission. Normally MSR bit-5 is the complement of the DSR# input. However in the
loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a
general purpose input when the modem interface is not used.
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS/DSR bit (EFR bit-6=1) and RTS/DTR flow control select bit (MCR bit-2=0). Auto CTS/DSR flow control
allows starting and stopping of local data transmissions based on the modem CTS# signal. A HIGH on the
CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW
will resume data transmission. Normally MSR bit-4 is the complement of the CTS# input. However in the
loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a
general purpose input when the modem interface is not used.
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
4.10
Modem Status Register (MSR) - Write Only
The upper four bits [7:4] of this register set the delay in number of bits time for the auto RS-485 turn around
from transmit to receive.
MSR[7:4]
When Auto RS-485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks. Table 17 shows the selection. The bits are enabled by EFR bit-4.
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