REV. 1.0.3 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’.
參數(shù)資料
型號(hào)： XR16V2552IL-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 20/46頁(yè)
文件大小： 0K
描述： IC UART FIFO 16B DUAL 32QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 托盤(pán)
XR16V2552
27
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 11 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 11 shows the complete selections.
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
FCR BIT-7
FCR BIT-6
FCR BIT-5
FCR BIT-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER LEVEL
COMPATIBILITY
0
1
0
1
0
1
0
1
0
1
0
1
4
8
14
1
4
8
14
16C550,
16C2550,
16C2552,
16C554,
16C580
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
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