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參數(shù)資料
| 型號(hào)： | XR16V2552IL-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B DUAL 32QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS422 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 托盤 |
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XR16V2552
33
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
4.11
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 13 below and SEE”PROGRAMMABLE BAUD
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 13 below.
TABLE 13: SAMPLING RATE SELECT
SAMPLING RATE
0
16X
0
1
8X
1
X
4X
DLD[7:6]: Reserved
4.12
Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
BIT-2
BIT-1
MF# FUNCTION
0
OP2# (default)
0
1
BAUDOUT#
1
0
RXRDY#
1
Reserved
AFR[7:3]: Reserved
All are initialized to logic 0.
4.13
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x02 for XR16V2552). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
DLD[5]
DLD[4]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V2650 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
| XR16V2650_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
| XR16V2650IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16V2650IL-0B-EB | 功能描述:UART 接口集成電路 Supports V2650 32pin QFN, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16V2650IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
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