- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16433 > XR16V798IQ-0B-EVB (Exar Corporation)EVAL BOARD FOR XR16V798-B 100QFP PDF資料下載
參數(shù)資料
| 型號： | XR16V798IQ-0B-EVB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 4/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR16V798-B 100QFP |
| 設(shè)計(jì)資源： | XR17V798/794 Eval Board Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
XR16V798
12
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
2.8
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X (or the 8X) clock for timing. It verifies and
validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or
false start bit, an internal receiver counter starts counting the number of 16X (or 8X) clocks. After 8 (or 4)
clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is
still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false
character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent
false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the
receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to
reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon
receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is
guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined
by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by
IER bit-0.
2.8.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 7. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16V798IQ-0A-EVB | EVAL BOARD FOR XR16V798-A 100QFP |
| XR16V698IQ-0B-EVB | EVAL BOARD FOR XR16V698-B 100QFP |
| XR16V698IQ-0A-EVB | EVAL BOARD FOR XR16V698-A 100QFP |
| KIT33972AEWEVBE | KIT EVALUATION FOR MC33972 |
| EBM31DCMS | CONN EDGECARD 62POS .156 WW |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V798IQ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16V798IQTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 2.5V/3.3V 100-Pin PQFP T/R |
| XR-1790 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Schematic |
| XR17C152 | 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS DUAL UART |
| XR17C152CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:5V PCI BUS DUAL UART |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。