NOTE
參數(shù)資料
型號: XR16V798IQ-0B-EVB
廠商: Exar Corporation
文件頁數(shù): 5/56頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR16V798-B 100QFP
設(shè)計資源: XR17V798/794 Eval Board Schematic
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16V798
13
REV. 1.0.1
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
NOTE: Table-B selected as Trigger Table for
2.9
THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 are shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Clock
E
rror
T
a
gs
(64-
s
e
ts)
Er
ro
rTa
gs
i
n
LSR
bi
ts
4
:2
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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