REV. 1.2.2 28 4.1.2 Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and" />
參數(shù)資料
型號: XR17D158CV-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 21/73頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17D158 144TQFP
標準包裝: 1
系列: *
XR17D158
xr
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
REV. 1.2.2
28
4.1.2
Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780
The XR17D158 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2), ....., 0xF80 (channel 3). The
entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD
reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following
tables show this clearly.
4.1.3
Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700, 0x900, 0xB00, 0xD00, 0xF00
The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2),
............, 0xD00 (channel 6) and 0xF00 (channel 7).
READ RX FIFO,
WITH LSR
ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
WRITE TX FIFO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 7 ReceiveData in 32-bit alignment through the Configuration Register Address
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 7 Receive Data with Line Status Register in a 32-bit alignment through the Configuration
Register Address 0x0180, 0x0380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80
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