REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 45 FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level" />
參數(shù)資料
型號(hào): XR17D158CV-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 40/73頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17D158 144TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
xr
XR17D158
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
45
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receiv-
er FIFO interrupt. Table 15 shows the complete selections. Note that the receiver and the transmitter cannot
use different trigger tables. Whichever selection is made last applies to both the RX and TX side.
TABLE 15: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
TRIGGER
TABLE
FCTR
BIT-7
FCTR
BIT-6
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
Table A
0
1
0
1
0
1
0
1 (default)
4
8
14
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580 compati-
ble.
Table B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
24
28
16
8
24
30
16C650A compati-
ble.
Table C
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
16C654 compati-
ble.
Table D
1
X
Programmable Programmable 16C850, 16C2850,
16C2852, 16C854,
16C864, 16L2750,
16L2751, 16L2752
compatible.
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