參數(shù)資料
型號： EVAL-ADAU1442EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 1/93頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1442
標準包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 電路板，線纜，說明文檔，GPIO 子板，電源
SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
Data Sheet
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2010–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to fS = 192 kHz
Multichannel byte-addressable TDM serial port
Pool of 170 ms digital audio delay (at 48 kHz)
Clock oscillator for generating master clock from crystal
PLL for generating core clock from common audio clocks
I2C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: 40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear-seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial audio processing
FUNCTIONAL BLOCK DIAGRAM
PROGRAMMABLE AUDIO
PROCESSOR CORE
S/PDIF
TRANSMITTER
S/PDIF
RECEIVER
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL CLOCK
DOMAINS
(×12)
CLOCK
OSCILLATOR
MP/
AUX ADC
PLL
I2C/SPI CONTROL
INTERFACE
AND SELF-BOOT
XTALI XTALO
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
SPI/I2C* SELFBOOT
SPDIFI
SPDIFO
CLKOUT
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
FLEXIBLE AUDIO ROUTING MATRIX
(FARM)
SERIAL DATA
INPUT PORT
(×9)
SERIAL DATA
OUTPUT PORT
(×9)
1.8V
REGULATOR
07696-
001
MP[11:4]
MP[3:0]/
ADC[3:0]
*SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
ADAU1442/
ADAU1445/
ADAU1446
Figure 1.
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