參數(shù)資料
型號(hào)： XR17D158CV
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
中文描述： 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù)： 41/72頁(yè)
文件大?。?/td> 1520K
代理商： XR17D158CV
xr
REV. 1.2.1
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
XR17D158
41
IER[4]: Reserved
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS#/DTR# Output Interrupt Enable (requires EFR bit-4=1)
The RTS# or DTR# output is selected via MCR bit-2. See
Table 11
or MCR[2] for complete details.
Logic 0 = Disable the RTS#/DTR# interrupt (default).
Logic 1 = Enable the RTS#/DTR# interrupt. The UART issues an interrupt when the RTS#/DTR# pin makes
a transition.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
The CTS# or DSR# input is selected via MCR bit-2. See
Table 11
or MCR[2] for complete details.
Logic 0 = Disable the CTS#/DSR# interrupt (default).
Logic 1 = Enable the CTS#/DSR# interrupt. The UART issues an interrupt when CTS# pin makes a transi-
tion.
5.8.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR
will give the user the current highest pending interrupt level to be serviced with others queued up for next ser-
vice. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table,
Table 14
, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associ-
ated with each of these interrupt levels.
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by the a 4-char plus 12 bits delay timer if the RX FIFO level is less than the RX trigger
level.
TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control).
MSR is by any of the MSR bits, 0, 1, 2 and 3.
Receive Xon
/
Xoff/Special character is by detection of a Xon, Xoff or Special character.
CTS#/DSR# is by a change of state on the input pin (from LOW to HIGH) with auto flow control enabled,
EFR bit-7, and depending on selection of MCR bit-2.
RTS#/DTR# is when its receiver changes the state of the output pin (from LOW to HIGH) during auto RTS/
DTR flow control enabled by EFR bit-6 and selection of MCR bit-2.
Wake-up Indicator: when the UART comes out of sleep mode.
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
TXRDY interrupt is cleared by a read to the ISR register.
MSR interrupt is cleared by a read to the MSR register.
Xon or Xoff character interrupt is cleared by a read to ISR register.
Special character interrupt is cleared by a read to ISR register or after the next character is received.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
Wake-up Indicator is cleared by a read to the INT0 register.
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