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參數(shù)資料
| 型號： | XR17D158CV |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART |
| 中文描述： | 8 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144 |
| 文件頁數(shù)： | 42/72頁 |
| 文件大?。?/td> | 1520K |
| 代理商： | XR17D158CV |
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XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
xr
REV. 1.2.1
42
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source
Table 14
).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. Reading the
XCHAR register will indicate which character (Xoff or Xon) was received last. If it is a special character
interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from LOW to HIGH.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
5.8.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode (legacy term that refers to "block transfer mode"). The DMA and FIFO modes are
defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive
FIFO
reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
T
ABLE
14: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
P
RIORITY
ISR R
EGISTER
S
TATUS
B
ITS
S
OURCE
OF
THE
INTERRUPT
L
EVEL
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
0
1
0
0
RXRDY (Received Data Ready)
3
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
4
0
0
0
0
1
0
TXRDY (Transmitter Holding Register Empty)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xon/Xoff or Special character)
7
1
0
0
0
0
0
CTS#/DSR#, RTS#/DTR# change of state
X
0
0
0
0
0
1
None (default)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XR17D158CV-0A-EVB | 功能描述:界面開發(fā)工具 Supports D158 144 ld TQFP, PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR17D158CV-F | 功能描述:UART 接口集成電路 3.3V-5V 64B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17D158CV-F-SIWI | 制造商:Exar Corporation 功能描述:FOR WILLIAMS GAMING THEIR CM'S 制造商:EXAR 功能描述:XR17D158CV-F-SIWI 制造商:EXAR 功能描述:FOR WILLIAMS GAMING THEIR CM'S |
| XR17D158CVTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17D158CVTR-F |
| XR17D158IV | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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