參數(shù)資料
型號(hào)： XR17L152CM
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 3.3V PCI BUS DUAL UART
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 11/55頁(yè)
文件大?。?/td> 318K
代理商： XR17L152CM
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
11
1.2.1
The XR17L152 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is a 2-bit indicator in INT0 register representing the 2
channels with the first 3 bits representing each channel from 0 to 1. This permits the interrupt routine to quickly
vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port
status requires service. INT0 bit-1 provides interrupt status for channel 1 and bits 2 to 7 are reserved and
remain at a logic 0.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code per channel. This 3-bit code represents 7 interrupts corresponding to individual
UART’s transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 6-bit interrupt
status for both channels. Bits 8, 9 and 10 represents channel 0 and bits 11,12 and 13 represents channel 1.
Bits 14 to 31 are reserved and remain at logic zero. Both channels interrupt status are available with a single
DWORD read operation. This feature allows the
host to quickly vector and serve the interrupts, reducing
service interval, hence, reducing host bandwidth requirements.
The Interrupt Status Register
Upon power-up or reset, all bits are a logic 0. A special interrupt condition is generated by the L152 upon
awakening from sleep after both channels were put to sleep mode earlier.
Figure 4
shows the 4-byte interrupt
register and its make up.
INT0 [7:0] Channel Interrupt Indicator.
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-1
indicates channel 1. Logic one indicates the channel N [1:0] has requested for service. Bits 2 to 7 are reserved
and remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting
channel register, see Interrupt Clearing section.
Ox091
MPIO3T
Read/Write MPIO output control
Bits 7-0 = 0x00
Ox092
MPIOINV
Read/Write MPIO input polarity select
Bits 7-0 = 0x00
Ox093
MPIOSEL
Read/Write MPIO select
Bits 7-0 = 0xFF
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
A
DDRESS
R
EGISTER
B
YTE
3 [31:24]
B
YTE
2 [23:16]
B
YTE
1 [15:8]
B
YTE
0 [7:0]
0x080
-
083
INTERRUPT (read-only)
INT3
INT2
INT1
INT0
0x084-087
TIMER (read/write)
TIMERMSB
TIMERLSB
TIMER
(reserved)
TIMERCNTL
0x088-08B
ANCILLARY1 (read/write)
SLEEP
RESET
REGA
(reserved)
8XMODE
0x08C-08F
ANCILLARY2 (read-only)
MPIOINT
REGB
DVID
DREV
0x090-093
MPIO (read/write)
MPIOSEL
MPIOINV
MPIO3T
MPIOLVL
GLOBAL INTERRUPT REGISTER (DWORD) [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
T
ABLE
3: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
BYTE
ALIGNMENT
A
DDRESS
[A7:A0]
R
EGISTER
R
EAD
/W
RITE
C
OMMENT
R
ESET
S
TATE
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