參數(shù)資料
型號(hào)： XR17L152CM
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 3.3V PCI BUS DUAL UART
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 32/55頁(yè)
文件大?。?/td> 318K
代理商： XR17L152CM
á
DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
32
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# output pin makes a
transition from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# input pin makes a transition
low to high.
Interrupt Status Register (ISR)
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table,
Table 12
, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by the a 4-char plus 12 bits delay timer.
TXRDY is by LSR bit-5 in the non-FIFO mode, TX trigger level setting in the FIFO mode (or bit-6 in auto
RS485 control).
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xon
/
Xoff/Special character is by detection of a Xon, Xoff or Special character.
CTS#/DSR# is by a change of state on the input pin (from low to high) with auto flow control enabled, EFR
bit-7, and depending on selection on MCR bit-2.
RTS#/DTR# is when its receiver changes the state of the output pin (from low to high) during auto RTS/DTR
flow control enabled by EFR bit-6 and selection of MCR bit-2.
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register (but LSR status bits are not cleared).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by emptying the RX FIFO.
TXRDY interrupt is cleared by a read to the ISR register.
MSR interrupt is cleared by a read to the MSR register.
Xon, Xoff or Special character interrupt is cleared by a read to ISR register.
RTS#/DTR# and CTS#/DSR# input status change interrupt is cleared by a read to the MSR register.
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