TABLE 8: UART CHANNEL [1:0] I
參數(shù)資料
型號(hào)： XR17V352IB-0A-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 10/64頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V352 113BGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
已用 IC / 零件： XR17V352
已供物品： 板
其它名稱： 1016-1610
1016-1610-ND
1016-1645
XR17V352IB-0A-EVB-ND
TABLE 8: UART CHANNEL [1:0] INTERRUPT CLEARING
Wake-up Indicator is cleared by reading the INT0 register.
RXRDY and RXRDY Time-out is cleared by reading data in the RX FIFO.
RX Line Status interrupt clears after reading the LSR register that is in the UART channel register set.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel reg-
ister set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
XR17V352
18
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. 1.0.3
1.4.2
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
The XR17V352 has a general purpose 16-bit timer/counter. The internal 125MHz clock or the external clock at
the TMRCK input pin can be selected as the clock source for the timer/counter. The timer can be set to be a
single-shot for a one-time event or re-triggerable for a periodic signal. An interrupt may be generated when the
timer times out and will show up as a Channel 0 interrupt (see Table 7). It is controlled through 4 configuration
registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. The TIMERCNTL register provides the Timer
commands such as start/stop, as shown in Table 9 below. The time-out output of the Timer can also be
optionally routed to the MPIO[0] pin. The block diagram of the Timer/Counter circuit is shown below:
FIGURE 5. TIMER/COUNTER CIRCUIT
Timer Interrupt
Timer
Output
MPIOLVL[0]
0
1
0
1
Timer Interrupt
No Interrupt
MPIO[0]
TMRCK
125MHz/62.5MHz
TIMERCNTL
COMMANDS
16-Bit
Timer/Counter
Start/Stop
Timer Interrupt Enable/ Disable
Single shot/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
Clock Select
Route/De-route to MPIO[0]
TIMERMSB [31:24] and TIMERLSB [23:16] registers
The concatentaion of the 8-bit registers TIMERMSB and TIMERLSB forms a 16-bit value which decides the
time-out period of the Timer, per the following equation:
Timer output frequency = Timer input clock / 16-bit Timer value
The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Notice that these registers do not hold the current counter value when read. Default value is zero
(timer disabled) upon powerup and reset. The ’Reset Timer’ command does not have any effect on this
register.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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XR17V354IB-0A-EVB 功能描述:界面開發(fā)工具 Eval Board for XR17V354IB-0A RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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