
XR17V352
14
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. 1.0.3
TABLE 4: XR17V352 UART AND DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
COMMENT
0x0000 - 0x000F
UART channel 0 Regs
First 8 regs are 16550 compatible
0x0010 - 0x007F
Reserved
0x0080 - 0x009A
DEVICE CONFIGURATION REGISTERS
(
0x009B - 0x00FF
Reserved
0x0100 - 0x01FF
UART 0 – Read FIFO
Read-Only
256 bytes of RX FIFO data
0x0100 - 0x01FF
UART 0 – Write FIFO
Write-Only
256 bytes of TX FIFO data
0x0200 - 0x03FF
UART 0 – Read FIFO with errors
Read-Only
256 bytes of RX FIFO data + LSR
0x0400 - 0x040F
UART channel 1 Regs
First 8 regs are 16550 compatible
0x0410 - 0x047F
Reserved
0x0480 - 0x049A
DEVICE CONFIGURATION REGISTERS
(
0x049B - 0x04FF
Reserved
0x0500 - 0x05FF
UART 1 – Read FIFO
Read-Only
256 bytes of RX FIFO data
0x0500 - 0x05FF
UART 1 – Write FIFO
Write-Only
256 bytes of TX FIFO data
0x0600 - 0x07FF
UART 1 – Read FIFO with errors
Read-Only
256 bytes of RX FIFO data + LSR