FIGURE 10. AUTO RTS/DTR
參數(shù)資料
型號: XR17V352IB-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 29/64頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR17V352 113BGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
已用 IC / 零件: XR17V352
已供物品:
其它名稱: 1016-1610
1016-1610-ND
1016-1645
XR17V352IB-0A-EVB-ND
FIGURE 10. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
XR17V352
35
REV. 1.0.3
HIGH PERFORMANCE DUAL PCI EXPRESS UART
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