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參數(shù)資料
型號： XR19L212IL48-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 23/52頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L202 48QFN
標準包裝： 1
系列： *
XR19L212
3
REV. 1.0.1
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
NAME
48-QFN
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
28
29
30
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
6
5
4
47
46
45
44
43
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(NC)
18
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
IOW#
(R/W#)
16
I
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
CSA#
(CS#)
10
I
When I/M# pin is HIGH, this input is chip select A (active low) to enable channel A in the
device.
When I/M# pin is LOW, this input becomes the chip select (active low) for the Motorola bus
interface.
CSB#
(A3)
11
I
When I/M# pin is HIGH, this input is chip select B (active low) to enable channel B in the
device.
When I/M# pin is LOW, this input becomes address line A3 which is used for channel selec-
tion in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects chan-
nel B.
INTA
(IRQ#)
32
O
(OD)
When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
HIGH device interrupt output for channel A. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output for both channels. An external pull-up resistor is required
for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
INTB
(NC)
31
O
(OD)
When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
HIGH device interrupt output for channel B. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output is not used and can
be left unconnected.
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