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參數(shù)資料
| 型號： | XR19L212IL48-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 8/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR19L202 48QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR19L212
16
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
NOTE: Table-B selected as Trigger Table for
2.13
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control feature
is enabled to fit specific application requirement (see Figure 11):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS
pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.14
Auto RTS Hysteresis
The L212 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the programmed RX trigger level. The RTS pin will not be de-
asserted until the receive FIFO reaches the upper limit of the hysteresis level. The RTS pin will be re-asserted
after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described conditions,
the L212 will continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when
the RTS output pin is asserted. Table 13 shows the complete details for the Auto RTS Hysteresis levels.
Please note that this table is for programmable trigger levels only (Table D). The hysteresis values for Tables
A-C are the next higher and next lower trigger levels in the corresponding table.
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
rro
rTag
s
(6
4-
set
s
)
Er
ro
rTag
s
in
LSR
bi
ts
4:2
64 bytes by 11-bit
wide FIFO
Receive Data Characters
FIFO Trigger=16
Example:
- RX FIFO trigger level selected at 16 bytes
(See Note below)
Data fills to 24
Data falls to 8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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| XR19L212IL48-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR19L212IL48TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 5V 48-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR19L212IL48TR-F |
| XR19L220 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L220_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L220IL40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
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