REV. 1.0.3 time will have a jitter (+/- 1/16) whenever the DLD is non-zero an" />
參數(shù)資料
型號(hào): XR19L400IL40-0B-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 2/46頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR19L202 40QFN
標(biāo)準(zhǔn)包裝: 1
系列: *
XR19L400
10
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-
standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16X mode EMSR[7] = 1
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode EMSR[7] = 0
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
The closest divisor that is obtainable in the L400 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 6. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X
Sampling
Rate Clock
to Transmitter
and Receiver
Fractional Baud
Rate Generator
Logic
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