REV. 1.0.3 FCTR[3]: Auto Half-Duplex Direction Control This bit overrides the" />
參數(shù)資料
型號(hào)： XR19L400IL40-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 28/46頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR19L202 40QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR19L400
34
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
FCTR[3]: Auto Half-Duplex Direction Control
This bit overrides the HALF/FULL# pin to enable half-duplex mode or full-duplex mode.
Logic 0 = Full-duplex mode. In this mode, the transmit interrupt is generated when the transmit holding
register becomes empty and the transmit shift register is shifting data out.
Logic 1 = Auto half-duplex mode. In this mode, the direction of the RS-485 transceiver is internally controlled
by the RTS# signal. Also, the transmit interrupt generation is delayed until the transmitter shift register
becomes empty.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
TABLE 12: TRIGGER TABLE SELECT
BIT-5
BIT-4
TABLE
0
Table-A (TX/RX)
0
1
Table-B (TX/RX)
1
0
Table-C (TX/RX)
1
Table-D (TX/RX)
Table 8 for more details.
FCTR[6]: Scratchpad Swap
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
If using both programmable TX and RX trigger levels, TX trigger levels must be set before RX trigger levels.
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
4.19
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 13). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
FCTR
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