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REV. 1.0.0 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS LSR[4]: Receive Break Tag

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參數(shù)資料

型號(hào)：	XR20M1280L32-0A-EB
廠商：	Exar Corporation
文件頁(yè)數(shù)：	33/63頁(yè)
文件大?。?/td>	0K
描述：	EVAL BOARD FOR XR20M1280L32
產(chǎn)品培訓(xùn)模塊：	XR21V141x Full-Speed USB UART Family UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝：	1
主要目的：	接口，UART
已用 IC / 零件：	XR20M1280L32
已供物品：	板
其它名稱：	1016-1630

XR20M1280

REV. 1.0.0

I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

LSR[4]: Receive Break Tag

Logic 0 = No break condition (default).

Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX

input returns to the idle condition, “mark” or HIGH.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte

is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0

concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set

when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

Logic 0 = No FIFO error (default).

Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

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