REV. 1.0.0 PIN DESCRIPTIONS Pin Description N" />
參數(shù)資料
型號: XR20M1280L32-0A-EB
廠商: Exar Corporation
文件頁數(shù): 34/63頁
文件大小: 0K
描述: EVAL BOARD FOR XR20M1280L32
產(chǎn)品培訓模塊: XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標準包裝: 1
主要目的: 接口,UART
已用 IC / 零件: XR20M1280L32
已供物品:
其它名稱: 1016-1630
XR20M1280
4
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
NAME
QFN-24
PIN#
QFN-32
PIN#
QFN-40
PIN#
TYPE
DESCRIPTION
I2C (SPI) INTERFACE
I2C/SPI#
24
1
I
I2C-bus or SPI interface select. I2C-bus interface is selected if this
pin is HIGH. SPI interface is selected if this pin is LOW
SDA
(GND)
2
4
I/O
I2C-bus data input/output (open-drain). If SPI configuration is
selected, then this pin should be tied LOW.
SCL
3
5
I
I2C-bus or SPI serial input clock.
When the I2C-bus interface is selected, the serial clock idles HIGH.
When the SPI interface is selected, the serial clock idles LOW.
IRQ#
4
6
OD
Interrupt output (open-drain, active LOW).
A0
(CS#)
6
8
I
I2C-bus device address select A0 or SPI chip select. If I2C-bus con-
figuration is selected, this pin along with the A1 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI chip select pin (Schmitt-trigger, active LOW).
A1
(SI)
5
7
I
I2C-bus device address select A1 or SPI data input pin. If I2C-bus
configuration is selected, this pin along with A0 pin allows user to
change the device’s base address. If SPI configuration is selected,
this pin is the SPI data input pin.
SO
(NC)
1
3
O
SPI data output pin. If I2C-bus configuration is selected, this pin
must be left unconnected.
RESET#
7
9
10
I
Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will
reset the internal registers and all outputs. The UART transmitter
output will be idle and the receiver input will be ignored.
MODEM I/O and GPIOs
TX
13
28
36
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
RX
14
29
37
I
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
RTS#
15
27
35
O
UART Request-to-Send (active low) or general purpose output. This
output must be asserted prior to using auto RTS flow control, see
EFR[6], MCR[1] and IER[6].
CTS#
12
26
34
I
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
GPIO0/DTR#
20
25
33
I/O
General purpose I/O or UART Data-Terminal-Ready (active low).
GPIO1/DSR#
19
24
32
I/O
General purpose I/O or UART Data-Set-Ready (active low).
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