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參數(shù)資料
型號: XR88C681CP/40-F
廠商: Exar Corporation
文件頁數(shù): 44/101頁
文件大小: 0K
描述: IC UART CMOS DUAL 40PDIP
標準包裝: 9
特點: *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
其它名稱: 1016-1328-5
XR88C681
47
Rev. 2.11
(e.g., AD0 - AD15 becomes D0 - D15, A16/S3 - A19/S6
becomes S3 - S6). A second group of multiplexed pins is
controlled by the MN/-MX input pin. When this pin is high,
the “min” mode is selected and pins 24 through 31 take on
the control definitions shown under the MN/-MX = 1
column in
Table 14. When the 8086 P operates in this
mode, it presents a control bus very similar to that of the
8085 P, and requires only an address latch and a clock
generator to form a CPU module.
Pin Number
MN/-MX = 1 (Min Mode)
MN/-MX = 0 (Max Mode)
24
HOLD
-
RQ/-GT0
25
HLDA
-
RQ/-GT1
26
-
WR
-
LOCK
27
M/-IO
-
S2
28
DT/R
-
S1
29
-
DEN
-
S0
30
ALE
QS0
31
-
INTA
QS1
Table 14. MN/-MX Mode and Function of Pins 24-31 of 8086 CPU Device.
When MN/-MX is low, the 8086 P is operating in the “max”
mode.
This mode is intended for more complex
applications in which the 8086 P requires support from
the 8087 numeric data processor (NDP). In this mode, a
special bus controller (the 8288) is required to generate
the memory and I/O control bus signals.
The 8086 P contains two interrupt request inputs: INTR
and NMI. NMI is the active-high “non-maskable” interrupt
request input; and INTR is the “maskable” interrupt
request input. If the 8086 P is operating in the “min”
mode, then the -INTA (Interrupt Acknowledge) pin is
available on Pin 24 (see
Figure 20). However, if the
8086 P is operating in the “max” mode, then the -INTA
signal must be derived from the -S0, -S1, and -S2 pins via
the 8288 bus controller.
Table 15 presents the processor
status and 8288 active outputs based on the -S0, -S1, and
-
S2 “max” mode status signals.
-
S2
-
S1
-
S0
Processor State
8288 Active Output
0
Interrupt Acknowledge
-
INTA
0
1
Read I/O Port
-
IORC
0
1
0
Write I/O Port
-
IOWC
0
1
Halt
None
1
0
Code Access
-
MRDC
1
0
1
Read Memory
-
MRDC
1
0
Write Memory
-
MWTC
1
Passive
None
Table 15. 8086 Processor State/8288 Bus Controller Active Output as a function of -S0, -S1 and -S2
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