參數(shù)資料
型號: XR88C681CP/40-F
廠商: Exar Corporation
文件頁數(shù): 66/101頁
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 40PDIP
標(biāo)準(zhǔn)包裝: 9
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
其它名稱: 1016-1328-5
XR88C681
67
Rev. 2.11
F.2 Output Port Configuration Register (OPCR)
The Output Port pins can be used as General Purpose Output pins, or they can be configured to used in alternate
functions.
Table 24 lists the Alternate Functions of each of the Output Port pins.
Output Port
Alternate Function(s)
OP0
-RTSA: Request-to-Send (RTS) output for Channel A. Note: This output is Active
Low for the RTS function.
OP1
-RTSB: Request-to-Send (RTS) output for Channel B. Note: This output is Active
Low for the RTS function.
OP2
TXCA_16X Output
: Channel A 16X Transmitter Clock Output.
TXCA_1X Output
: Channel A 1X Transmitter Clock Output.
RXCA_1X Outpu
t: Channel A 1X Receiver Clock Output.
OP3
TXCB_1X Output
: Channel B 1X Transmitter Clock Output.
RXCB_1X Output
: Channel B 1X Receiver Clock Output.
C/T_RDY
: The Counter/Timer Ready Output for C/T #1. Note: This output is an
Open-Drain output when used as the Counter/Timer Ready Output.
OP4
RXRDY/FFULL_A Output
: Channel A Receiver Ready/FIFO Full Indicator. Note:
This is an Open-Drain output for the RXRDY/FFULL_A function.
OP5
RXRDY/FFULL_B Output
: Channel B Receiver Ready/FIFO Full Indicator. Note:
This is an Open-Drain output for the RXRDY/FFULL_B function.
OP6
TXRDY_A Output
: Channel A Transmitter Ready Indicator. This is an Open-Drain
output for the TXRDY_A function.
OP7
TXRDY_B Output
: Channel B Transmitter Ready Indicator. This is an Open-Drain
output for the TXRDY_B function.
Table 24. Listing of the Alternate Functions for the Output Port
Many of the Alternate Functions of the various Output Port pins are selected by writing the appropriate data to the OPCR.
The bit format of this register follows
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OP7
OP6
OP5
OP4
OP3
OP2
0 = OPR[7]
1 = TXRDYB
0 = OPR[6]
1 = TXRDYA
0 = OPR[5]
1 = RXRDY/
FFULLB
0 = OPR[4]
1 = RXRDY/
FFULLA
00 = OPR[3]
01 = C/T #1 Output
10 = TXCB (1X)
11 = RXCB (1X)
00 = OPR[2]
01 = TXCA (16X)
10 = TXCA (1X)
11 = RXCA (1X)
Note:
OPCR only addresses the alternate functions for Output Port pins, OP7 - OP2. OP0 and OP1 assume their RTS roles if either
MR1n[7] = 1 or MR2n[5] = 1. Setting those Mode Register bits enables the RTS function. Otherwise, these two ports will only
be General Purpose Output Ports.
Table 25. Output Port Configuration Register - OPCR
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