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參數(shù)資料
| 型號： | XRD8799AIQ |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX |
| 中文描述： | 8-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 408K |
| 代理商： | XRD8799AIQ |
xr
XRD8799
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
10
F
IGURE
5. XRD8799 C
OMPARATORS
1.1
The transfer function for an ideal A/D converter is
shown in Figure 6.
A
CCURACY
OF
C
ONVERSION
: DNL
AND
INL
F
IGURE
6. I
DEAL
A/D T
RANSFER
F
UNCTION
The overflow transition (VOFW) takes place at:
V
IN
= VOFW = V
REF(+)
The first and the last transitions for the data bits take
place at:
V
IN
= V001 = V
REF(-)
+ 1.0 * LSB
V
IN
= V3FF = V
REF(-)
- 1.0 * LSB
V
REF
= V
REF(+)
-
V
REF(-)
LSB = V
REF
/ 1024 = (V
3FF
- V001) / 1022
N
OTE
:
The overflow transition is a flag and has no impact
on the data bits.
In a "real" converter the code-to-code transitions don't
fall exactly every V
REF
/1024 volts.
A positive DNL (Differential Non-Linearity) error
means that the real width of a particular code is larger
than 1 LSB. This error is measured in fractions of
LSBs.
A Max DNL specification guarantees that ALL code
widths (DNL errors) are within the stated value. A
specification of Max DNL = + 0.5 LSB means that all
code widths are within 0.5 and 1.5 LSB. If V
REF
=
4.608 V then 1 LSB = 4.5 mV and every code width is
within 2.25 and 6.75 mV.
Settle by Clock Update Time
Reference Stable Time - For Sample A
IN1
Sample AIN1
Reference Stable Time - For Sample A
IN2
Hold Reference Value Past
Clock Change for t
AP
Time
Short Cycle Sample will be discarded
Sample AIN2
AINX1
Not Used
A
IN
X0
Sample A
IN1
Sample A
IN2
Sample Ladder
for A
IN1
Sample Ladder
for A
IN
X1
Sample Ladder
for
AIN2
Sample Ladder
for A
IN
X2
Compare Ladder
V/S A
IN
X0
Compare Ladder
V/S A
IN1
Compare Ladder
V/S A
IN
X1
Compare Ladder
V/S A
IN2
DATA A
IN0
DATA A
IN
X0
DATA A
IN1
DATA A
IN
X1
Not Used
Not Used
DATA
Ladder Compare
(LSB Bank)
Ladder Sample
Window (MSB Bank)
AIN Sample
Window
Clock
Update
References
External
Internal
External
t
S
Φ
B
Φ
S
Φ
B
Φ
B
Φ
S
Φ
S
A
IN
X1
3FF
3FE
3FD
V
REF(-)
V
REF(+)
DIGITAL
CODES
000
002
LSB
OFW=0
V
001
OFW=1
1 LSB
V001
V002
V
3FE
V
3FF
V
0FW
=
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