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參數(shù)資料
| 型號： | XRD8799AIQ |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX |
| 中文描述： | 8-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 408K |
| 代理商： | XRD8799AIQ |
xr
XRD8799
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
14
2.0
APPLICATION NOTES
F
IGURE
16. T
YPICAL
C
IRCUIT
C
ONNECTIONS
The following information will be useful in maximizing
the performance of the XRD8799.
1. All signals should not exceed AV
DD
+0.5 V or
AGND -0.5 V or DV
DD
+0.5 V or DGND -0.5 V.
2. Any input pin which can see a value outside the
absolute maximum ratings (AV
DD
or DV
DD
+0.5 V
or AGND -0.5 V) should be protected by diode
clamps (HP5082-2835) from input pin to the sup-
plies. All XRD8799 inputs have input protection
diodes which will protect the device from short
transients outside the supply ranges.
3. The design of a PC board will affect the accuracy
of XRD8799. Use of wire wrap is not recom-
mended.
4. The analog input signal (V
IN
) is quite sensitive
and should be properly routed and terminated. It
should be shielded from the clock and digital out-
puts so as to minimize cross coupling and noise
pickup.
5. The analog input should be driven by a low
impedance (less than 50
).
6. Analog and digital ground planes should be sub-
stantial and common at one point only. The
ground plane should act as a shield for parasitics
and not a return path for signals. To reduce noise
levels, use separate low impedance ground
paths.
DGND should not be shared with other
digital circuitry
. If separate low impedance paths
cannot be provided, DGND should be connected
to AGND next to the XRD8799.
7.
DV
DD
should not be shared with other digital cir-
cuitry
to avoid conversion errors caused by digital
supply transients. DV
DD
for the XRD8799 should
be connected to AV
DD
next to the XRD8799.
8. DV
DD
and AV
DD
are connected inside the
XRD8799. DGND and AGND are connected
internally.
9. Each power supply and reference voltage pin
should be decoupled with a ceramic (0.1
μ
F) and
a tantalum (10
μ
F) capacitor as close to the
device as possible.
10. The digital output should not drive long wires.
The capacitive coupling and reflection will con-
tribute noise to the conversion. When driving dis-
tant loads, buffers should be used. 100
resis-
tors in series with the digital outputs in some
applications reduces the digital output disruption
of A
IN
.
OFW
CLK
DB9 - DB0
OE
AGND
DGND
(Substrate)
XRD8799
AIN1
V
REF(+)
V
REF(-)
3/4 R
1/4 R
Buffer
AV
DD
DV
DD
C1D, C2D
C1A, C2A
C1 = 4.7 or 10
μ
F Tantalum
C2 = 0.1
μ
F Chip Cap or low inductance cap
R
T
= Clock Transmission Line Termination
Reference
Voltage
Source
V
REF1(-)
A
IN
C1
C2
C1
C2
C1
C2
+
-
+5 V
R
T
1 of 8
AIN8
Z < 100
Resistive
Isolation of
50 to 100
WR
CLK
A2
A1
A0
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