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參數(shù)資料
| 型號： | XRD8799AIQ |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX |
| 中文描述： | 8-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 408K |
| 代理商： | XRD8799AIQ |
xr
XRD8799
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
12
F
IGURE
10. R
ELATIONSHIP
OF
D
ATA
TO
C
LOCK
1.3
The XRD8799 has very flexible input range character-
istics. The user may set V
REF(+)
and V
REF(-)
to two
fixed voltages and then vary the input DC and AC lev-
els to match the VREF range. Another method is to
first design the analog input circuitry and then adjust
the reference voltages for the analog input range.
One advantage is that this approach may eliminate
the need for external gain and offset adjust circuitry
which may be required by fixed input range A/Ds.
The XRD8799's performance is optimized by using
analog input circuitry that is capable of driving the A
IN
input. Figure 11 shows the equivalent circuit for A
IN
.
A
NALOG
I
NPUT
F
IGURE
11. A
NALOG
I
NPUT
E
QUIVALENT
C
IRCUIT
1.4
The XRD8799 includes a 8-Channel analog input
multiplexer. The relationship between the clock, the
multiplexer address, the
WR
and the output data is
shown in Figure 12.
A
NALOG
I
NPUT
M
ULTIPLEXER
F
IGURE
12. MUX A
DDRESS
T
IMING
F
IGURE
13. A
NALOG
MUX T
IMING
1.5
The input/output relationship is a function of V
REF
:
A
IN
= V
IN
- V
REF(-)
V
REF
= V
REF(+)
- V
REF(-)
DATA = 1024 * (A
IN
/V
REF
)
A system can increase total gain by reducing V
REF
.
R
EFERENCE
V
OLTAGES
CLOCK
DATA
b. Single sampling
N
N
BALANCE
CLOCK
DATA
a. Continuous sampling
N
N+1
N
N+1
50
10 pF
AV
DD
A
IN
80
φ
S
10 pF
160
4
1 pF
10 pF
Channel
Selection
8
Control
R Series
200
R MUX
200
1/2 [ V
REF(+)
+ V
REF(-)
]
φ
S
φ
B
1 pF
+
WR
Clock
DB0-DB9
t
CLKS2
t
WR
t
CLKH2
Address
t
AS
t
AH
Sample N
Old Address
Sample M
New Address
Sample
M+1
N-2 Valid
N-1 Valid
Old Address
N Valid
Old Address
M Valid
New Address
Note:
t
CLKS2
= t
CLKH2
= 0
A2, A1, A0
MUXEN
(Internal Signal)
t
AS
t
AH
WR
t
WR
t
MUXEN1
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