參數(shù)資料
型號(hào): XRD98L62
廠商: Exar Corporation
英文描述: CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
中文描述: 與綜合發(fā)展區(qū),和12的PGS CCD圖像數(shù)字轉(zhuǎn)換器,位A / D(防治荒漠化公約圖像數(shù)字轉(zhuǎn)換器(帶地帶素類和12位的A / D轉(zhuǎn)換器))
文件頁(yè)數(shù): 11/37頁(yè)
文件大小: 394K
代理商: XRD98L62
11
Rev. P2.00
XRD98L62
Preliminary
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset
Default
OB[7]
1
OB[6]
0
OB[5]
0
OB[4]
0
OB[3]
0
OB[2]
0
OB[1]
0
OB[0]
0
0
0
Offset Register (Reg. 1, Address 000001)
The Offset register is used to set the target ADC output code for Optical Black pixels.
See the Black Level Offset Calibration section for more information.
Table 1. Serial Interface Register Address Map & default values
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain
Default
PGA[9]
0
PGA[8]
0
PGA[7]
0
PGA[6]
0
PGA[5]
0
PGA[4]
0
PGA[3]
0
PGA[2]
0
PGA[1]
0
PGA[0]
0
The Gain register is used to set the gain of the Programmable Gain Amplifier (PGA).
Code 0000000000 is minimum gain (0 dB). Codes 1011111111 and greater are maximum gain (36 dB).
See the Programmable Gain Amplifier (PGA) section for more information.
Gain Register (Reg. 0, Address 000000)
Address bits
Data bits
D5
PGA[5]
0
OB[5]
0
LFrame
0
WL[7]
0
Reg. Name A5 A4 A3 A2 A1 A0
D9
D8
D7
D6
D4
D3
D2
D1
D0
Gain
0
0
0
0
0
0
PGA[9]
0
PGA[8]
0
PGA[7]
0
OB[7]
1
Avg[0]
1
WL[9]
0
PGA[6]
0
OB[6]
0
Mode
0
WL[8]
0
PGA[4]
0
OB[4]
0
DNS[1]
1
WL[6]
0
PGA[3]
0
OB[3]
0
DNS[0]
1
WL[5]
0
PGA[2]
0
OB[2]
0
FastCal
1
WL[4]
0
PGA[1]
0
OB[1]
0
Hold
0
WL[3]
0
WL[1]
0
OBL[1]
1
CDAC[1]
0
FDAC[1]
0
ADCpd
0
FRpol
0
RSTreject
0
DelayA[1]
0
DelayB[1]
0
DAC0[1]
0
DAC1[1]
0
PGA[0]
0
OB[0]
0
ManCal
0
WL[2]
0
WL[0]
1
OBL[0]
0
CDAC[0]
0
FDAC[0]
0
PwrDwn
0
ADCpol
0
VSreject
0
DelayA[0]
0
DelayB[0]
0
DAC0[0]
0
DAC1[0]
0
Offset
0
0
0
0
0
1
Calibration
0
0
0
0
1
0
Avg[2]
1
WL[11]
0
Avg[1]
0
WL[10]
0
Wait A
0
0
0
0
1
1
Wait B
0
0
0
1
0
0
OB Lines
0
0
0
1
0
1
OBL[7]
0
CDAC[7]
0
FDAC[7]
0
NoCDS
0
OBL[6]
0
CDAC[6]
0
FDAC[6]
0
LowPwr
0
OBL[5]
0
CDAC[5]
0
FDAC[5]
0
OE
1
SBLKpol
OBL[4]
0
CDAC[4]
0
FDAC[4]
0
DAC1pd
1
SPIXpol
0
OneShot
0
DelayA[4]
0
DelayB[4]
0
DAC0[4]
0
DAC1[4]
0
OBL[3]
0
CDAC[3]
0
FDAC[3]
0
DAC0pd
1
CALpol
0
ClampCal
0
DelayA[3]
0
DelayB[3]
0
DAC0[3]
0
DAC1[3]
0
OBL[2]
0
CDAC[2]
0
FDAC[2]
0
AFEpd
0
CLAMPpol
0
SPIXopt
0
DelayA[2]
0
DelayB[2]
0
DAC0[2]
0
DAC1[2]
0
CDAC
0
0
0
1
1
0
CDAC[8]
0
FDAC[8]
0
ADCtest
0
FDAC
0
0
0
1
1
1
FDAC[9]
0
DIGtest
0
Control
0
0
1
0
0
0
Polarity
0
0
1
0
0
1
0
Clock
0
0
1
0
1
0
CLKtest
0
nullamp
0
DelayA[8]
0
DelayB[8]
0
cmset
0
DelayA[7]
0
DelayB[7]
0
DAC0[7]
0
DAC1[7]
0
fastclk
0
DelayA[6]
0
DelayB[6]
0
DAC0[6]
0
DAC1[6]
0
CLAMPopt
0
Delay A
0
0
1
0
1
1
DelayA[5]
0
Delay B
0
0
1
1
0
0
DelayB[5]
0
DAC0
0
0
1
1
0
1
DAC0[5]
0
DAC1
0
0
1
1
1
0
DAC1[5]
0
ReadBack
1
1
1
1
1
0
RBenable
0
RBreg[8]
0
RBreg[7]
0
RBreg[6]
0
RBreg[5]
0
RBreg[4]
0
RBreg[3]
0
RBreg[2]
0
RBreg[1]
0
RBreg[0]
0
Reset
0
Reset
1
1
1
1
1
1
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