參數(shù)資料
型號(hào): XRD98L62
廠商: Exar Corporation
英文描述: CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
中文描述: 與綜合發(fā)展區(qū),和12的PGS CCD圖像數(shù)字轉(zhuǎn)換器,位A / D(防治荒漠化公約圖像數(shù)字轉(zhuǎn)換器(帶地帶素類和12位的A / D轉(zhuǎn)換器))
文件頁(yè)數(shù): 21/37頁(yè)
文件大?。?/td> 394K
代理商: XRD98L62
21
Rev. P2.00
XRD98L62
Preliminary
CDS
12-bit ADC
Hot Pixel
Clipper
Pixel
Averager
+
-
+
Coarse
Accumulator
Fine
Accumulator
Offset Calibration Logic
12
PGA
Reg
Hold, FastCal
DNS[1:0]
OB[7:0]
PGA[9:0]
DB[11:0]
C
F
+
+
Black Level
Offset Calibration
Loop
ManCAL
CDAC, FDAC
From Serial
Interface
Registers
CCD
signal
OB Lines[7:0]
Wait[11:0]
DNS
Filter
Black Level Offset Calibration
Figure 8. Black Level Offset Calibration Block Diagram
Chip Reset
The chip includes a Power-On-Reset function (POR)
so when the power supplies are turned on the chip will
always power up with default values in all registers.
There are two methods to force a chip reset. The first
is to write a “1” to the RESET bit in the reset register.
This will reset the chip, and after a delay of about 10
ns, the reset bit will automatically clear itself. The
second reset method is to force the RESET pin high.
This will reset the chip until the RESET pin goes low
again. The RESET pin has an internal pull down.
相關(guān)PDF資料
PDF描述
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
XRK32308CD-1 3.3V ZERO DELAY BUFFER
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