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參數(shù)資料
| 型號： | XRD98L62 |
| 廠商： | Exar Corporation |
| 英文描述： | CCD Image Digitizers with CDA，PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器（帶CDA，PGS和12位A/D轉(zhuǎn)換器）) |
| 中文描述： | 與綜合發(fā)展區(qū)，和12的PGS CCD圖像數(shù)字轉(zhuǎn)換器，位A / D（防治荒漠化公約圖像數(shù)字轉(zhuǎn)換器（帶地帶素類和12位的A / D轉(zhuǎn)換器）） |
| 文件頁數(shù)： | 14/37頁 |
| 文件大小： | 394K |
| 代理商： | XRD98L62 |
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XRD98L62
14
Rev. P2.00
Preliminary
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Clock
Default
CLKtest Nullamp CMtest Fastclk CLAMPopt Oneshot ClampCal
0
0
0
0
SPIXopt
0
RSTreject VSreject
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay A
Default
DelayA[8]
0
DelayA[7]
0
DelayA[6]
0
DelayA[5]
0
DelayA[4]
0
DelayA[3]
0
DelayA[2]
0
DelayA[1]
0
DelayA[0]
0
0
Delay A Register (Reg. 11, Address 001011)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Delay B
Default
DelayB[8]
0
DelayB[7]
0
DelayB[6]
0
DelayB[5]
0
DelayB[4]
0
DelayB[3]
0
DelayB[2]
0
DelayB[1]
0
DelayB[0]
0
0
DelayB Register (Reg. 12, Address 001100)
The DelayA & DelayB registers are used to add internal delay to the pixel rate clocks.
For each 3 bit delay parameter, 000 is minimum delay, 111 is maximum delay (
～
7ns).
DelayA[8:6]: ADC Clock delay.
DelayA[5:3]:
φ1
trailing edge delay.
DelayA[2:0]:
φ
1 leading edge delay.
DelayB[8:6]: Delay for SPIX option.
DelayB[5:3]:
φ
2 trailing edge delay.
DelayB[2:0]:
φ
2 leading edge delay.
Clock Register (Reg. 10, Address 001010)
The Clock register is used to set various clocking options.
CLKtest=0, Please leave this bit in the default setting.
Nullamp=0, Please leave this bit in the default setting.
CMtest=0, Please leave this bit in the default setting.
Fastclk=0, Please leave this bit in the default setting.
CLAMPopt=0, DC Restore bias is on only during CLAMP.
CLAMPopt=1, DC Restore bias is always ON.
OneShot=0, CAL defines OB pixels. Clamp controls DC restore.
OneShot=1, CAL controls DC restore and defines OB pixels. CLAMP used for VS reject.
ClampCal=0, CLAMP at start of line, CAL at end of line (affects VS reject).
ClampCal=1, CAL at start of line, CLAMP at end of line (affects VS reject).
SPIXopt=0,
φ
2 starts DelayA[5:3] + DelayB[8:6] after SBLK trailing edge
SPIXopt=1,
φ
2 starts DelayB[2:0] after SPIX pin leading edge.
RSTreject=0, Reset reject switch (
φ
3) not clocked, always on.
RSTreject=1, Reset reject switch (
φ
3) clocked.
VSreject=0, Vertical Shift Reject is inactive.
VSreject=1, Vertical Shift Reject is active.
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| XRDAN30 | CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications |
| XRK32308_07 | 3.3V ZERO DELAY BUFFER |
| XRK32308CD-1 | 3.3V ZERO DELAY BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L62ACV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L62ACV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRD98L62EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62ZEVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
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