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參數(shù)資料
| 型號： | XRD98L62 |
| 廠商： | Exar Corporation |
| 英文描述： | CCD Image Digitizers with CDA，PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器（帶CDA，PGS和12位A/D轉(zhuǎn)換器）) |
| 中文描述： | 與綜合發(fā)展區(qū)，和12的PGS CCD圖像數(shù)字轉(zhuǎn)換器，位A / D（防治荒漠化公約圖像數(shù)字轉(zhuǎn)換器（帶地帶素類和12位的A / D轉(zhuǎn)換器）） |
| 文件頁數(shù)： | 25/37頁 |
| 文件大小： | 394K |
| 代理商： | XRD98L62 |
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25
Rev. P2.00
XRD98L62
Preliminary
Pipeline Delay
The digital outputs, DB[11:0] and OVER, are synchro-
nized to ADCLK. When ADCLKpol=0 (default), the
digital outputs change on the rising edge of ADCLK.
Figure 14 shows the pipeline delay (latency) from
sampling a pixel at the CDS input, until the
coresponding data is available at the digital output.
Pixel Rate CLOCKS
SBLK, SPIX & ADCLK
Note:
The timing descriptions in this section are correct for
the default conditions: All Polarity bits = 0,
RSTreject = 0 (switch always ON),
SPIXopt = 0
Sampling of the pixel Black Level is controlled by the
SBLK pulse. When SBLK is low, the internal sample
Black switches in the CDS are ON, sampling the pixel
black level on the internal capacitors.
The AFE starts tracking the pixel Video Level an
internal delay after the rising edge of SBLK. The
internal delay is programmed by DelayB[8:6]. The
AFE holds the pixel Video Level on the rising edge of
SPIX.
SBLK
SPIX
CCD
Signal
t
PIX
ADCLK
DB[11:0]
t
BK
t
VD
t
DL
t
PW1
t
PW2
Black Sample Point
Video Sample Point
Figure 13.
Detailed Pixel Rate Clock Timing for Default Register Settings
The ADC will track the PGA output when ADCLK is
high. The ADC will hold the PGA output and start a
conversion when ADCLK goes low. The falling edge of
ADCLK should happen coincident with, or just before
the rising edge of SBLK. ADCLK should be as close as
possible to 50% duty cycle.
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| XRDAN28 | Frequency Response Effects of Overampling and Averaging on A/D Output Data |
| XRDAN29 | Criteria for Accurate Sampling of Analog Signals |
| XRDAN30 | CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications |
| XRK32308_07 | 3.3V ZERO DELAY BUFFER |
| XRK32308CD-1 | 3.3V ZERO DELAY BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L62ACV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L62ACV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRD98L62EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62ZEVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
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