參數(shù)資料
型號: XRD98L62ACV
廠商: EXAR CORP
元件分類: 消費家電
英文描述: CCD Image Digitizers with CDS, PGA and 12-Bit A/D
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
文件頁數(shù): 13/37頁
文件大?。?/td> 286K
代理商: XRD98L62ACV
13
Rev. P2.00
XRD98L62
Preliminary
D9
D8
D7
D6
D5
OE
1
D4
D3
D2
D1
D0
Control
Default
DIGtest
0
ADCtest
0
NoCDS
0
LowPwr
0
DAC1pd DAC0pd
1
AFEpd
0
ADCpd
0
PwrDwn
0
1
FDAC
FDAC[9]
FDAC[8]
FDAC[7]
FDAC[6]
FDAC[5]
FDAC[4]
FDAC[3]
FDAC[2]
FDAC[1]
FDAC[0]
Default
0
0
0
0
0
0
0
0
0
0
FDAC Register (Reg. 7, Address 000111)
The FDAC register is used to set the Fine Offset DAC in the Manual Calibration mode.
See Calibration
Option, in the Black Level Offset Calibration section for more information.
Control Register (Reg. 8, Address 001000)
The Control register is used to set various test and power-down modes.
DIGtest=0, please leave this bit in the default setting.
ADCtest=0, connects PGA output to ADC input.
ADCtest=1, connects ADCinP & ADCinN pins to ADC input.
NoCDS=0, connects CDS output to PGA input.
NoCDS=1, connects Test1 & Test2 pins to PGA inputs (CDS by-pass mode).
Low Power=0, selects the normal, 12 bit ADC mode.
Low Power=1, selects the low power, 6 bit ADC mode.
OE=0, digital outputs in high-Z state.
OE=1, digital outputs enabled.
DAC1pd=1, Utility DAC1 is powered down.
DAC0pd=1, Utility DAC0 is powered down.
AFEpd=1, CDS & PGA are powered down, do not use.
ADCpd=1, ADC is powered down, do not use.
PwrDwn=1, the whole chip is powered down.
Polarity Register (Reg. 9, Address 001001)
The Polarity register is used to set the polarity for the 6 input clock signals.
For each clock: polarity bit=0 sets clock active low, polarity bit=1 sets clock active high.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Polarity
Default
SBLKpol SPIXpol
0
CALpol
0
CLAMPpol FRpol ADCpol
0
0
0
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CDAC
Default
CDAC[8] CDAC[7] CDAC[6] CDAC[5] CDAC[4] CDAC[3] CDAC[2] CDAC[1] CDAC[0]
0
0
0
0
0
0
0
0
0
0
CDAC Register (Reg. 6, Address 000110)
The CDAC register is used to set the Coarse Offset DAC in the Manual Calibration mode.
See Calibration Option, in the Black Level Offset Calibration section for more information.
相關(guān)PDF資料
PDF描述
XRD98L62 CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
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