參數(shù)資料
型號(hào): XRD98L62ACV
廠(chǎng)商: EXAR CORP
元件分類(lèi): 消費(fèi)家電
英文描述: CCD Image Digitizers with CDS, PGA and 12-Bit A/D
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
文件頁(yè)數(shù): 15/37頁(yè)
文件大?。?/td> 286K
代理商: XRD98L62ACV
15
Rev. P2.00
XRD98L62
Preliminary
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
Default
Reset Register (Reg. 63, Address 111111)
Reset
0
0
0
0
0
0
0
0
0
0
The Reset register is used to reset the entire chip.
Reset=0, Normal operation.
Reset=1, Resets the chip. The Reset bit will automatically reset after approximately 10 ns delay.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC0
Default
DAC0[7] DAC0[6] DAC0[5] DAC0[4] DAC0[3] DAC0[2] DAC0[1] DAC0[0]
0
0
0
0
0
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC1
Default
DAC1[7] DAC1[6] DAC1[5] DAC1[4] DAC1[3] DAC1[2] DAC1[1] DAC1[0]
0
0
0
0
0
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ReadBack RBenable
Default
RBreg[8] RBreg[7] RBreg[6] RBreg[5] RBreg[4] RBreg[3] RBreg[2] RBreg[1] RBreg[0]
0
0
0
0
0
0
0
0
0
0
Readback Register (Reg. 62, Address 111110)
The readback register is used to enable the readback
function and select a register for readback.
RBenable=0, Readback disabled.
RBenable=1, Readback enabled. Contents of se-
lected register is output on DB[11:2] pins.
RBreg[8:0], select register to read from, see table in
Serial Interface Read Back section.
DAC1 Register (Reg. 14, Address 001110)
The DAC1 & DAC0 registers are used to program
the two 8-bit Utility DACs.
Code 00000000 is minimum output voltage.
Code 11111111 is maximum output voltage.
DAC0 Register (Reg. 13, Address 001101)
相關(guān)PDF資料
PDF描述
XRD98L62 CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
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