參數(shù)資料
型號(hào): XRD98L62ACV
廠商: EXAR CORP
元件分類: 消費(fèi)家電
英文描述: CCD Image Digitizers with CDS, PGA and 12-Bit A/D
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
文件頁數(shù): 31/37頁
文件大?。?/td> 286K
代理商: XRD98L62ACV
31
Rev. P2.00
XRD98L62
Preliminary
One Shot (CAL Only) Mode
In this mode, the CAL signal is used to activate the DC
restore clamp and to define the optical black pixels for
calibration. The CAL pulse should frame the longest
group of OB pixels at either the end or beginning of
each line. The DC restore Clamp switch is turned ON
during the first four pixels of each CAL pulse. The
remaining pixels under the CAL pulse are used for
black level calibration.
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels
Vertical Shift
Dummy &
OB pixels
CAL
(Black Level)
CLAMP
(DC restore)
CCD
Signal
Active Video pixels
t
CAL
t
CLAMP
Vert. Shift Reject
(internal)
Disconnect CDS from
input pins
Figure 21. Line Rate Timing with OneShot=0, VSreject=1 & ClampCal=1
This mode also has an option to disconnect the CDS
from the input pins during the Vertical Shift time. To
enable this option write a “1” to the VSreject bit in the
Clock register. The signal at the CLAMP pin is used to
define the Vertical Shift period (i.e. the time when the
CDS is disconnected from the input pins).
相關(guān)PDF資料
PDF描述
XRD98L62 CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
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