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參數(shù)資料
| 型號： | XRD98L62ACV |
| 廠商： | EXAR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48 |
| 文件頁數(shù)： | 17/37頁 |
| 文件大?。?/td> | 286K |
| 代理商： | XRD98L62ACV |
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17
Rev. P2.00
XRD98L62
Preliminary
Correlated Double Sample/Hold (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA then amplifies this difference to
the desired level for the ADC. The CDS and PGA are
fully differential. The CCDin pin should be connected,
via a capacitor, to the CCD output signal. The REFin
pin should be connected, via a capacitor, to the CCD
“Common” voltage (typically the CCD ground is used
as the “Common” voltage). These capacitors, C1 and
C2, are typically 0.01
μ
F + 10% or better matching.
The timing for the switches shown in Figure 5 are
determined by
φ
1,
φ
2, and
φ
3.
φ
1,
φ
2, and
φ
3 are
internally generated from the timing signals SBLK and
SPIX shown in Figures 17 & 18.
φ
3 (reset reject
switches) are closed to simplify the operation de-
scribed below.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capaci-
tors to an internal bias level (Vbias1=1.2V). The DC
restore switch is controlled by the combination of the
CLAMP input signal ANDed with the
φ
2 clock.
During the black reference phase of each CCD pixel the
φ
1 (Sample Black Reference) switches are turned on,
shorting the PGA1 inputs to a second bias level
(Vbias2). The Coarse Offset DAC adds an adjustment
to the bias level (Vbias2) to cancel black level offset in
the CCD signal. When the
φ
1 switches turn off, the
pixel black reference level is sampled on the internal
black sample capacitors, and the PGA is ready to gain
up the CCD video signal.
During the video phase of each CCD pixel the differ-
ence between the pixel black level and video level is
transmitted through the internal black sample capaci-
tors and converted to a fully differential signal by the
PGA1 amplifier. At this time the
φ
2 (Sample Pixel
value) switches turn on, an the internal video sample
capacitors track the amplified difference. The Fine
Offset DAC adds offset adjustment to the PGA2 output
(post gain).
φ
1
φ
2
CLAMP
φ
2
Vbias1=1.2V
Vbias2
REFin
CCDin
PGA1
PGA2
CCD
Coarse
Offset
DAC
PGA
CDS
External
DC Blocking
Capacitors
Internal
Black Sample
Capacitors
φ
3
Internal
Video Sample
Capacitors
DC Restore Switches
C1
C2
Fine
Offset
DAC
Figure 5. CDS and PGA Block Diagram
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L62ACV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRD98L62EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62ZEVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L63AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
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