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參數(shù)資料
| 型號： | XRT71D04IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER |
| 中文描述： | DATACOM, PCM JITTER ATTENUATOR, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 254K |
| 代理商： | XRT71D04IV |
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XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
13
1.2.1
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming sig-
nal that it can receive in an error-free manner.
1.2.2
Jitter Generation
Jitter generation is defined in Section 7.3.3 of GR-
499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of mapping
and pointer adjustment jitter generation.
Mapping jitter is the sum of the intrinsic payload map-
ping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchro-
nous DSn mapping into STS SPE.
1.2.3
Jitter Attenuation
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the refer-
ence clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
Jitter Tolerance
In Figure 5and Figure 6, this de-jittered clock is la-
beled Smoothed Clock. This Smoothed Clock is now
used to Read Out the Recovered Data from the 16/32
bit FIFO. This Smoothed Clock will also be output to
the Terminal Equipment via the RRClk output pin.
Likewise, the Smoothed Recovered Data will output
to the Terminal Equipment via the RRPOS and
RRNEG output pins.
The XRT71D03 is designed to work as a companion
device with XRT73L03 (STS-1/DS3/E3) Line Inter-
face Unit.
ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when mea-
sured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compli-
ant with the standard. ITU G.751 is another applica-
tion where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multi-
plexer system.
1.2.4
SONET STS-1 DS3 Mapping
Bellcore GR-253 section 3.4.2 and the ANSI T1.105-
199 describes the asynchronous mapping for DS3 in-
to STS-1 SPE.
F
IGURE
7. C
ATEGORY
1 DS3 J
ITTER
T
RANSFER
M
ASK
0.1
J
(
Acceptable
Range
40
Frequency (Hz)
slope = -20 dB/decade
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| XRT71D04IVTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 4CH E3/DS3/STS1 JIT ATTEN DE-SYNCH RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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| XRT7288 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
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