參數(shù)資料
型號(hào): XRT71D04IV
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
中文描述: DATACOM, PCM JITTER ATTENUATOR, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁(yè)數(shù): 22/22頁(yè)
文件大?。?/td> 254K
代理商: XRT71D04IV
á
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
20
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2001 EXAR Corporation
Datasheet April 2001.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
Rev. P1.0.1; Revised pull-up/pull-down resistors on various pins.
Rev. P1.0.2; Changed date and made minor edits to page 1.
Rev. P1.0.3; Corrected Pin List descriptions. Modified pin names to be consistant, ie MCLK0, RPOS0,
RNEG0, etc. changed to MCLK_0, RPOS_0, RNEG_0, etc. Changed VSS to GND. Changed figures to re-
flect pin name changes.
Rev. 1.1.0 Removed preliminary designation. Added electrical tables.
Rev. 1.1.1 Corrected Table 4 adding RRClkES_n as data D2, STS-1_n as D5, added D7. Corrected the
description of the section 3 Serial Microprocessor Interface. Moved figure 9 into Electrical Characteristics
Section. Moved Jitter Transfer/Tolerance tables into Jitter Attenuator Section 1.
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