參數(shù)資料
型號(hào)： XRT71D04IV
廠商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
中文描述： DATACOM, PCM JITTER ATTENUATOR, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁(yè)數(shù)： 5/22頁(yè)
文件大小： 254K
代理商： XRT71D04IV
á
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.0
3
11
MODE_CTRL
I
Mode Control:
When “High” in Multimode, all channels are independent. When “Low”, the
Master Channel (channel0) controls DS3/E3_n, STS1_n, RCLKES, FSS and
MCLKn. DJA is NOT affected.
Internal 50 K Ohm pull-up resistor.
12
ICT
I
In Circuit Testing Input.
(Active low):
With this pin tied to ground, all output pins will be in high impedance mode for
in-circuit-testing.
For normal operation this input pin should be tied to VDD.
Internal 50 K Ohm pull-up resistor.
13
HOST
I
Host/Hardware Mode Select:
An active-high input enables the Host mode. Data is written to the command
registers to configure the XRT71D04.
In the Host mode, the states of discrete input pins are inactive.
An active-low input enables the Hardware Mode.In this mode, the discrete
inputs are active.
Internal 50 K Ohm pull-down resistor.
14
FLRST
I
Fifo Limit Reset
Hardware Mode
Whenever the FIFO is within 2 bits of either underflow or overflow, the FLn) will
be set high.
This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin.
This pin when pulsed “High”, resets the the FL_n output pin, (toggles to GND).
N
OTE
:
The FL_n could be set “High” again if the FIFO is within 2 bits of either
underflow or overflow.
Host Mode
Reading the FL_n bits in the status registers clears the FL_n pin. Master
RESET also clears the FL_n output.
This pin is tied to GND. FLRST has no effect in this mode.
Internal 50 K Ohm pull-down resistor.
15
GND
****
Digital Ground
16
NC
No Connection
17
AGND
****
Analog Ground
18
FL_0
O
FIFO Limit - channel 0:
This output pin is driven high whenever the internal FIFO comes within two-bits
of being underflow or overflow.
19
STS1_0
I
SONET STS1 Mode Select - channel 0:
This pin along with the DS3/E3_0 select pin configures the XRT71D03 either in
E3, DS3 or STS-1 mode.
A table relating to the setting of the pins is given below:
STS-1
DS3/E3
XRT71D03 Operating Mode
0 0 DS3 (44.736 MHz)
0 1 E3 (34.368 MHz)
1 0 STS-1 (51.84 MHz)
1 1 E3 (34.368 MHz)
This input pin is active only in the Hardware Mode
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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