參數(shù)資料
型號(hào)： XRT71D04IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
中文描述： DATACOM, PCM JITTER ATTENUATOR, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 254K
代理商： XRT71D04IV
á
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
F
EATURES
................................................................................................................................................... 1
A
PPLICATIONS
............................................................................................................................................. 1
Figure 1. Block Diagram (one Channel) ................................................................................................ 1
Figure 2. Pin Out of the XRT71D03 ........................................................................................................ 2
ORDERING INFORMATION ..................................................................................................................... 2
TABLE OF CONTENTS...................................................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 2
ELECTRICAL CHARACTERISTICS ................................................................................... 8
Figure 3. Input/Output Timing ................................................................................................................ 8
Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................... 9
SYSTEM DESCRIPTION ................................................................................................... 11
Figure 5. Illustration of a typical Channel_n of the XRT71D03 configured to operate in the Hardware
Mode ........................................................................................................................................ 11
Figure 6. Illustration of of a typical Channel_n of the XRT71D03 (configured to operate in the Host
Mode) ....................................................................................................................................... 12
1.0 Jitter Attenuator PLL .............................................................................................................................. 12
1.1 B
ACKGROUND
I
NFORMATION
:.....................................................................................................................................12
1.1.1 Definition of Jitter ..........................................................................................................................................12
1.1.2 SONET STS-1 to DS3 Mapping...................................................................................................................12
1.2 J
ITTER
T
RANSFER
C
HARACTERISTICS
.........................................................................................................................12
Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 13
1.2.1 Jitter Tolerance .............................................................................................................................................13
1.2.2 Jitter Generation............................................................................................................................................13
1.2.3 Jitter Attenuation ...........................................................................................................................................13
1.2.4 SONET STS-1 DS3 Mapping.......................................................................................................................13
Figure 8. XRT71D03 Desynchronizer Block Diagram ........................................................................ 14
1.3 XRT71D03 J
ITTER
T
RANSFER
AND
T
OLERANCE
.........................................................................................................15
T
ABLE
1: XRT71D03 J
ITTER
T
RANSFER
F
UNCTION
.................................................................................. 15
T
ABLE
2: XRT71D03 M
AXIMUM
J
ITTER
T
OLERANCE
................................................................................. 16
2.0 Operating Modes .................................................................................................................................... 16
2.1 H
ARDWARE
M
ODE
.....................................................................................................................................................16
T
ABLE
3: F
UNCTIONS
OF
DUAL
MODE
PINS
IN
H
ARDWARE
M
ODE
CONFIGURATION
..................................... 16
2.2 H
OST
M
ODE
.............................................................................................................................................................16
T
ABLE
4: A
DDRESS
AND
B
IT
F
ORMATS
OF
THE
C
OMMAND
R
EGISTERS
...................................................... 17
3.0 Microprocessor Serial Interface ............................................................................................................ 17
3.1 S
ERIAL
I
NTERFACE
O
PERATION
..................................................................................................................................17
3.1.1 Bit 1—R/W (Read/Write) Bit..........................................................................................................................17
3.1.2 Bits 2 through 5—A0, A1, A2 ,A3,and A4 .....................................................................................................17
3.1.3 Bit 7—A5.......................................................................................................................................................17
3.1.4 Bit 8—A6.......................................................................................................................................................17
3.1.5 Read Operation.............................................................................................................................................17
3.1.6 Write Operation.............................................................................................................................................17
Figure 9. Microprocessor Serial Interface Data Structure ................................................................. 18
3.1.7 Simplified Interface Option............................................................................................................................18
Figure 10. Timing Diagram for the Microprocessor Serial Interface ................................................ 18
ORDERING INFORMATION ............................................................................................. 19
PACKAGE DIMENSIONS ................................................................................................. 19
R
EVISION
H
ISTORY
..................................................................................................................................... 20
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