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XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.7
4
PIN DESCRIPTION CONNECTED PINS
PIN #PIN NAME
TYPE
DESCRIPTION
A1
TxLev[1]
O
Transmit Line Build-Out Enable/Disable Select output pin - Chan-
nel 1:
See Description for Pin C3
A2
EncoDis[1]
O
HDB3/B3ZS Encoder Enable/Disable output pin - Channel 1:
See Description for Pin B2
A3
RxOOF[0]
O
Receive Out of Frame Indicator - Channel 0:
The Receive Section of Channel 0, within the XRT72L53 Framer IC will
assert this output signal whenever it has declared an Out of Frame
(OOF) condition with the incoming DS3 or E3 frames. This signal is
negated when the framer correctly locates the framing alignment bits or
bytes and correctly aligns itself with the incoming DS3 or E3 frames.
A4
RxRed[1]
O
Receive Red Alarm Indicator - Channel 1:
See Description for Pin B5
A5
REQ[0]
O
Receive Equalization Enable/Disable Select output pin - Channel 0-
(to be connected to the DS3/E3 Line Interface Unit IC):
This output pin is intended to be connected to either the REQ, REQDIS
or REQEN input pin of the DS3/E3 LIU. The user can control the state
of this output pin by writing a '0' or '1' to Bit 5 (REQ) within the Line
Interface Driver Register (Address = 0x80).
This output pin permits the user to have control over the state of the
Receive Equalizer block(s) within the corresponding DS3/E3 LIU IC.
Writing a "1" to Bit 5 of the Line Interface Drive Register (Address =
0x80) will cause this output pin to toggle "High". Writing a "0" to this bit-
field will cause this output pin to toggle "Low".
NOTE: This output pin can also be used as a “General Purpose Output”
pin.
A6
LLOOP[1]
O
Local Loop-back Output pin - Channel 1 (to be connected to the
LLOOP input pin of the DS3/E3 LIU IC):
See Description for Pin C7
A7
RLOOP[1]
O
Remote Loop-back Output pin - Channel 1 (to be connected to the
RLOOP input pin of the DS3/E3 LIU IC):
See Description for Pin B7
A8
ExtLOS[1]
I
Receive LOS (Loss of Signal) Input - Channel 1:
See Description for Pin D9
A9
RxOHClk[1]/
RxHDLCClk[1]
O
Receive Overhead Data Output Clock signal/Receive HDLC Con-
troller Output Clock signal - Channel 1:
See Description for Pin D12
A10
TxOHClk[1]
O
Transmit Overhead Clock Output - Channel 1:
See Description for Pin A14
A11
TxOHFrame[1]/
TxHDLCClk[1]
O
Transmit Overhead Framing Pulse/Transmit HDLC Controller Out-
put clock signal - Channel 1:
See Description for Pin C13
A12
TxOH[1]/
TxHDLCDat5[1]
I
Transmit Overhead Input pin/Transmit HDLC Controller Data Input
- Bit 5 (Channel 1):
See Description for Pin A15