參數(shù)資料
型號(hào)： XRT73LC00
廠商： Exar Corporation
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： E3/DS3/STS-1線路接口單元
文件頁(yè)數(shù)： 3/53頁(yè)
文件大?。?/td> 604K
代理商： XRT73LC00
á
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1. Block Diagram of the XRT73L00 ....................................................................................................... 1
ORDERING INFORMATION ............................................................................................... 2
Figure 2. Pin Out of the XRT73L00 in the 44 Pin TQFP ................................................................................... 2
PIN DESCRIPTION ............................................................................................................. 3
ELECTRICAL CHARACTERISTICS ................................................................................. 11
DC E
LECTRICAL
C
HARACTERISTICS
............................................................................................................ 11
AC E
LECTRICAL
C
HARACTERISTICS
............................................................................................................ 12
Figure 3. Timing Diagram of the Transmit Terminal Input Interface ............................................................... 13
Figure 4. Timing Diagram of the Receive Terminal Output Interface ............................................................. 13
AC ELECTRICAL CHARACTERISTICS (CONT’D) L
INE
S
IDE
P
ARAMETERS
........................................... 14
ABSOLUTE MAXIMUM RATINGS ................................................................................................... 16
Figure 5. Transmit Pulse Amplitude Test Circuit for DS3, E3 and STS-1 Rates ............................................ 17
Figure 6. ITU-T G.703 Transmit Output Pulse Template for E3 Applications ................................................. 17
Figure 7. Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications ............................ 18
Figure 8. Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ........... 18
AC ELECTRICAL CHARACTERISTICS (CONT.) ................................................................................... 19
Figure 9. Timing Diagram for the Microprocessor Serial Interface ................................................................. 19
SYSTEM DESCRIPTION ................................................................................................... 20
T
HE
T
RANSMIT
S
ECTION
............................................................................................................................ 20
T
HE
R
ECEIVE
S
ECTION
.............................................................................................................................. 20
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................................ 20
T
ABLE
1: R
OLE
OF
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
PINS
WHEN
THE
XRT73L00
IS
OPERATING
IN
THE
H
ARD
-
WARE
M
ODE
...................................................................................................................................... 20
1.0 Selecting the Data Rate ............................................................................................. 21
T
ABLE
2: S
ELECTING
THE
D
ATA
R
ATE
FOR
THE
XRT73L00
VIA
THE
E3
AND
STS-1/DS3
INPUT
PINS
(H
ARDWARE
M
ODE
) ............................................................................................................................................... 21
C
OMMAND
R
EGISTER
CR4 (A
DDRESS
= 0
X
04) ........................................................................................... 21
T
ABLE
3: S
ELECTING
THE
D
ATA
R
ATE
FOR
THE
XRT73L00 V
IA
THE
STS-1/DS3
AND
THE
E3 B
IT
-
FIELDS
W
ITHIN
C
OM
-
MAND
R
EGISTER
CR4 (HOST M
ODE
) ................................................................................................. 21
2.0 The Transmit Section ................................................................................................ 22
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
.............................................................................................................. 22
Figure 10. The Typical Interface for the Transmission of Data in a Dual-Rail Format From the Transmitting Ter-
minal Equipment to the Transmit Section of the XRT73L00 ........................................................ 22
Figure 11. How the XRT73L00 Samples the Data on the TPDATA and TNDATA Input Pins ........................ 22
2.1.1 Accepting Single-Rail Data from the Terminal Equipment ................................................. 23
C
OMMAND
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) ........................................................................................... 23
Figure 12. The Behavior of the TPDATA and TCLK Input Signals While the Transmit Logic Block is Accepting
Single-Rail Data From the Terminal Equipment ........................................................................... 23
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
...................................................................... 23
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
.................................................................................................... 24
2.3.1 B3ZS Encoding ....................................................................................................................... 24
Figure 13. An Example of B3ZS Encoding ..................................................................................................... 24
2.3.2 HDB3 Encoding ...................................................................................................................... 24
Figure 14. An Example of HDB3 Encoding .................................................................................................... 25
2.3.3 Enabling/Disabling the HDB3/B3ZS Encoder ...................................................................... 25
2.4 T
HE
T
RANSMIT
P
ULSE
S
HAPER
C
IRCUITRY
........................................................................................... 25
C
OMMAND
R
EGISTER
CR2 (A
DDRESS
= 0
X
02) ........................................................................................... 25
2.4.1 Enabling the Transmit Line Build-Out Circuit ...................................................................... 25
2.4.2 Disabling the Transmit Line Build-Out Circuit ..................................................................... 25
C
OMMAND
R
EGISTER
CR1 (A
DDRESS
= 0
X
01) ........................................................................................... 25
REV. 1.2.0
I
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