參數(shù)資料
型號： XRT73LC00
廠商： Exar Corporation
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： E3/DS3/STS-1線路接口單元
文件頁數(shù)： 43/53頁
文件大小： 604K
代理商： XRT73LC00
á
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
40
If the XRT73L00 is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the LLB bit-field and a “0” into the RLB bit-
field in Command Register 4.
If the XRT73L00 is operating in the Hardware
Mode:
The LLB input pin (pin 14) must be set to “High” and
the RLB input pin (pin 15) must be set to “Low”.
N
OTES
:
1. The Analog Local Loop-Back Mode does not work
if the transmitter is turned off via the TXOFF fea-
ture.
2. The XRT73L00 automatically Declares an LOS
Condition anytime it has been configured to oper-
ate in either the Analog Local Loop-Back or Digital
Local Loop-Back Modes. Consequently, the MUT-
ing -upon -LOS must be disabled prior to configur-
ing the device to operate in either of these local
Loop-Back modes.
T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
When the XRT73L00 is configured to operate in the
Digital Local Loop-Back Mode, it ignores any signals
that are input to the RTIP and RRING input pins. The
Transmitting Terminal Equipment transmits clock and
data into the XRT73L00 via the TPDATA, TNDATA
and TCLK input pins. This data is processed through
the Transmit Clock Duty Cycle Adjust PLL and the
HDB3/B3ZS Encoder block and then looped back to
the HDB3/B3ZS Decoder block.
Figure 29 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
4.2
The Digital Local Loop-Back Mode, along with the Tx-
OFF feature, is useful in Redundancy System De-
sign. These two features permit the system to exe-
cute some diagnostic tests in the Back-up Line Card
without transmitting data onto the line and interfering
with the DS3/E3/STS-1 traffic from the Primary Line
Card.
The XRT73L00 can be configured to operate in the
Digital Local Loop-Back Mode by employing either
one of the following two-steps.
A. If the XRT73L00 is operating in the HOST
Mode
Access the Microprocessor Serial Interface and write
a “1” into both the LLB and RLB bit-fields in Com-
mand Register 4.
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
1
0
F
IGURE
29. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
IN
THE
XRT73L00
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2
RPOS
RNEG
DR/SR
RLOS
LLB
RLB
ENDECDIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
相關(guān)PDF資料
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